1. Field of the Invention
The present invention relates to a semiconductor device having a multilayered wiring structure and a method of manufacturing the same and, more particularly, to a semiconductor device in which different wiring layers are connected to each other via a through-hole, and a method of manufacturing the same.
2. Description of the Related Art
A conventional method of manufacturing a semiconductor device having a multilayered wiring structure in which respective wiring layers are connected to each other via a through-hole will be described below with reference to FIGS. 1A to 1D. As shown in FIG. 1A, a silicon oxide film 32 as an insulating interlayer is formed on a silicon substrate 31 by a CVD (Chemical Vapor Deposition) method. Subsequently, a first aluminum layer is deposited on the entire surface of the silicon oxide film 32 and patterned to form a first wiring layer 33.
As shown in FIG. 1B, a thick silicon oxide film 34 is formed on the entire surface of the resultant structure at a low temperature of 300.degree. C. to 380.degree. C. by a plasma CVD method. Subsequently, as shown in FIG. 1C, the silicon oxide film 34 formed on the first wiring layer 33 is selectively removed by an RIE (Reactive Ion Etching) method using a predetermined mask, thereby forming a through-hole 35. Thereafter, a second aluminum layer is deposited on the entire surface and patterned to form a second wiring layer 36.
In the above conventional method, however, upon formation of the through-hole performed by RIE in the step shown in FIG. 1C, a formation position of the through-hole 35 may be deviated from a correct position on the first wiring layer 33, as shown in a plan view of FIG. 2, due to a mask misalignment or a process variation. If the through-hole 35 is deviated from the correct position in this manner, the silicon oxide film 32 is etched to a portion located below the first wiring layer 33. In this case, a leakage current is produced between the second wiring layer 36 and an underlying polycrystalline silicon wiring layer (not shown) or the silicon substrate 31, or inconveniences such as a short circuit occur in the worst case.
When the second wiring layer 36 is etched to be deviated from the through-hole 35, the first wiring layer 33 is etched to cause a reliability or disconnection defect.
In order to form a through-hole, therefore, as shown in a plan view of FIG. 3, the wiring width of the first wiring layer 33 at a prospective formation position of the through-hole 35 is set to be much larger than a minimum width of the first wiring layer. That is, a predetermined size margin which can allow a mask misalignment or a process variation is set between the through-hole 35 and the first wiring layer 33. As a result, the above inconveniences do not occur even if the through-hole 35 is deviated from the prospective formation position.
When the wiring width of the first wiring layer at the prospective formation position of the through-hole is increased, as shown in FIG. 3, however, a wiring pitch is inevitably increased to lead to an increase in chip area.